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Instruction set architectures
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51	Under 100-cycle Thread Migration Latency in a Single-ISA Heterogeneous Multi-core Processor Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Brandon Dwiel, Rangeen Basu Roy Chowdhury, Vinesh Srinivasan, Steve Lipa, Er Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2015-08-21 02:18:29 Central processing unit Microprocessors Computer architecture Parallel computing Instruction set architectures Multi-core processor ARM architecture Microarchitecture ARM Cortex-A15 AMD 10h ARM big.LITTLE Processor register
52	Chapter 4 CPU Design Reading: The corresponding chapter in the 2nd edition is Chapter 5, in the 3rd edition it is Chapter 5 and in the 4th edition it is Chapter Add to Reading List Source URL: eceweb.ucsd.edu Language: English - Date: 2015-07-31 19:30:10 Instruction set architectures Central processing unit Instruction set Sign extension Datapath Classic RISC pipeline DLX
53	THE FIRST ENTERPRISE CLASS 64-BIT ARMV8 SERVER: HP MOONSHOT SYSTEM’S HP PROLIANT M400 SERVER CARTRIDGE A PPLIED M ICRO X-G ENE -B ASED S ERVER D EMONSTRATES 35% L OW ER TCO S CALE -O UT W EB T IER /C ACHING E NVIRONMEN Add to Reading List Source URL: www.moorinsightsstrategy.com Language: English - Date: 2014-09-29 08:04:28 Applied Micro Circuits Corporation Power Architecture Instruction set architectures ProLiant ARM architecture Standard Performance Evaluation Corporation HP Integrated Lights-Out Hypervisor Windows NT 64-bit computing Hewlett-Packard Linaro
54	Advanced Parallel Architecture Lesson 2 Annalisa Massini Introduction Add to Reading List Source URL: twiki.di.uniroma1.it Language: English - Date: 2015-03-03 11:01:50 Parallel computing Central processing unit Microprocessors Instruction set architectures Classes of computers Bit-level parallelism Reduced instruction set computing Instruction-level parallelism 64-bit computing Instruction set Very long instruction word Microarchitecture
55	OVERVIEW Scope AR collaborated with one of their large industrial clients to perform a side-‐by-‐ side comparison of Scope AR’s WorkLi Add to Reading List Source URL: www.scopear.com Language: English - Date: 2016-06-06 10:55:21 Central processing unit Computing Instruction set Software Computer Instruction set architectures
56	The Semantics of Power and ARM Multiprocessor Machine Code Jade Alglave2 Anthony Fox1 Samin Ishtiaq3 Magnus O. Myreen1 Add to Reading List Source URL: www0.cs.ucl.ac.uk Language: English - Date: 2012-09-10 07:41:00 Central processing unit Computer architecture Computer memory Parallel computing Instruction set architectures Memory barrier Processor register Instruction set ARM architecture ALGOL 68 CPU cache Computer data storage
57	Contacts: Jim Ormond Add to Reading List Source URL: awards.acm.org Language: English - Date: 2016-05-18 11:44:53 Classes of computers Instruction set architectures Microprocessors Computer architecture Parallel computing EckertMauchly Award John Mauchly Complex instruction set computing Association for Computing Machinery Superscalar processor Computer X86
58	Haifeng Niu Education -‐Current: Ph.D., Missouri University of Science and Technology, Rolla, US Add to Reading List Source URL: www.imscenter.net Language: English - Date: 2013-04-22 11:19:45 Instruction set architectures Automatic identification and data capture Privacy Radio-frequency identification Ubiquitous computing Wireless Robot ARM architecture Debugging Automation Texas Instruments TMS320
59	RISC-V on Sakura-G Advisor(s): Thomas Unterluggauer Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria Motivation Add to Reading List Source URL: www.iaik.tugraz.at Language: English - Date: 2015-09-08 06:00:03 Instruction set architectures Reconfigurable computing Fabless semiconductor companies Xilinx Field-programmable gate array RISC-V Reduced instruction set computing